Field
The present disclosure relates generally to multi-core computing systems, and more specifically to controlling operation of multiple cores in a multi-core system.
Background
With the advent of multiple processors or multiple cores on a single chip (also known as SoCs), processing tasks have been distributed to various processors or cores that specialize in a given function to provide enhanced performance. For instance, some smartphones now comprise a core for OS activities including audio decoding, a core for video decoding, a core for rendering and composing graphical frames, a core for composing frames, another core for handling WiFi data, and yet another core for telephony.
When processors such as those listed above are operating on a power constrained device (e.g., a device utilizing battery power), it is important for the processors to keep power consumption low while providing the performance benefits associated with multiple processors. To keep power consumption low, it is known that the frequency and voltage on a processor may be reduced when the processor is operating under reduced loads. Although some existing systems may reduce the frequency and voltage of a processor to save power, these systems are typically reactive in nature; thus adversely affecting both power and performance.
Referring to FIG. 1A for example, one approach for managing a processor includes the processor waiting for an idle time out before reducing the clock frequency and voltage. A disadvantage of this approach is that even after the completion of frame processing, the processor will wait for an idle timeout period before reducing frequency and voltage; thus adversely impacting power consumption. Another disadvantage is that the processor will not know when the next frame needs to be processed. As a consequence, there will be an increased power load that occurs due to the processor clock needing to be turned on to react to the increased processing requirements; thus adversely affecting performance.
Another approach depicted in FIG. 1B includes a processor waiting for a few frames before increasing or decreasing the frequency or voltage of the processor. As shown in this example, even though the processor is busy processing a frame, the processor waits for a few samples before increasing its frequency and voltage, but as shown, the increase in frequency may be too late to address the processing needs of the frame; thus adversely affecting performance. In addition, by virtue of waiting a few samples to react to a particular processing load, the frequency of the processor may be unnecessarily high; thus utilizing an increased level of power unnecessarily.
Another shortfall of current systems is a lack of a framework to detect a “bottleneck” that affects system performance. Referring to FIG. 1C, for example, a graphics processing unit (“GPU”) is depicted as taking an extended period of time to process a frame (shown as frame 1); thus the GPU in this example, is effecting a bottleneck in the system processing. To address this issue, current systems may increase an application processor's frequency so that the application processor may process the frame more quickly (to enable the GPU to start processing the frame sooner), but this workaround does not necessarily improve the bottleneck while it necessarily results in increased power consumption.
In short, existing approaches to reduce power consumption of processing cores are generally reactive in nature, which adversely affects performance, and these approaches are less than optimal in terms of power management.